Split gate non-volatile flash memory cells having a select gate, a floating gate, a control gate and an erase gate are well known in the art. See for example U.S. Pat. Nos. 6,747,310 and 7,868,375. An erase gate having an overhang over the floating gate is also well know in the art. See for example, U.S. Pat. No. 5,242,848. All three of these patents are incorporated herein by reference in their entirety.
In order to increase performance, the floating gate can be doped with impurities. For example, increasing the dopant level on the floating gate can increase the erase speed of the memory cell. However, there are drawbacks to increased doping. For example, out-diffuse of dopants from a highly doped floating gate can decrease the quality of the dielectric material surrounding the floating gate. Higher dopant levels can also cause the blunting of the floating gate tip during oxidation processes.
Accordingly, it is one of the objectives of the present invention to improve the erase efficiency of such a memory cell without relying on high levels of dopant in the floating gate.